Dynamic RAM circuits commonly supply a two-stage "boot" signal to drive their wordlines in order to improve DRAM performance. For example, U.S. Pat. Nos. 4,543,500 and 4,533,843 to McAlexander et al. contain disclosure of the advantages of booting the wordline of a DRAM above the supply voltage. In the first stage of the boot signal, the signal rises from a low voltage (ground) to a high voltage (the power supply voltage or "V.sub.cc "). In the second stage of the boot signal, the signal is "booted" or "boosted" above V.sub.cc in order to fully restore the charge in the DRAM cell which was previously read. As taught by U.S. Pat. Nos. 4,533,843 and 4,543,500, it is necessary to supply a voltage higher than V.sub.cc in order to fully charge the memory cell.
The two-stage boot signal is generated by a "booting circuit." The boot signal is output to a plurality of "pass gates", each pass gate being associated with a wordline. A "row decode" circuit selects one of the pass gates to pass the signal to its associated wordline, while the remainder of the pass gates remain in a high impedance state.
In previously developed pass gates, a transistor is used to pass the boot signal. Since the boot signal exceeds V.sub.cc in its second stage, the gate of the transistor must likewise exceed V.sub.cc. The large voltage present at the gate of the transistor results in large voltage differentials across the junctions of other transistors in the circuit, thus creating a potential for field-aided breakdown of those junctions. The possibility of field-aided breakdown of a transistor junction presents a reliability problem, as the characteristics of the affected transistor may change after repeated exposure to junction breakdown conditions.
Therefore, the need has arisen for a pass gate which increases the breakdown voltage limit of a transistor subject to field-aided breakdown.